This invention relates, in general, to differential amplifiers and, more particularly, to a circuit for reducing the offset voltage drift of a differential amplifier when the amplifier's offset voltage is trimmed.
An ideal differential amplifier has zero output voltage when the differential inputs thereto are equal. It is well known, however, that commercially-available differential amplifiers are far from ideal, giving rise to a finite offset voltage. This voltage is defined as the output voltage of the amplifier divided by its gain when the differential inputs are tied together. The offset voltage, which is a function of mismatched input transistors in the differential amplifier, causes an undesirable difference in the currents between the input and subsequent stages of the amplifier.
The offset voltage drift of a differential amplifier is a measure of the change in the offset voltage relative to changes in temperature. It is known in the prior art to provide an offset adjustment circuit which reduces the magnitude of the temperature-induced offset voltage drift after the offset voltage has been initially trimmed. An example of such a post-trim drift adjustment circuit is disclosed in U.S. Pat. No. 4,050,030 to Russell.
In the Russell patent, the offset adjustment circuit 14 includes a current source JFET 38 connected in series with a resistor 40 for establishing a biasing voltage for a pair of JFET's 42 and 44 connected to variable resistors 46 and 48, respectively. During the trimming portion of the operation, the currents through JFET's 42 and 44 are adjusted through variable resistors 46 and 48 to cancel the amplifier offset voltage via conductors 34 and 36. Any post-trim temperature variations will then change the conduction level of the JFET 38 such that the bias of JFET's 42 and 44 will also change. Specifically, any temperature change, which increases the offset voltage, also tends to increase the drain currents of JFET's 42 and 44 by an equal amount. Therefore, the offset voltage provided by the offset adjustment circuit remains independent of temperature such that the amplifier produces minimal post-trim offset voltage drift.
The adjustment circuit of the Russell patent is theoretically an efficient design for minimizing offset drift. However, in reality, the JFET pairs 42 and 44 and 22 and 24 therein tend to contribute to the amplifier offset voltage drift. Specifically, the JFET's produce a finite drift which results from the fact that the temperature coefficients of these adjustment components differ from the temperature coefficients of the input transistors being adjusted. Russell recognized this problem and provided that the temperature coefficients of the components of both the adjusting circuit and the input stage be theoretically equal. It is known, however, that even with the best manufacturing processes, JFET mismatch between two transistors on the same microchip can be as high as a few percent. Any mismatch between components in the offset adjustment circuit of the Russell patent will increase the overall amplifier offset voltage and offset voltage drift.
Another approach for reducing differential amplifier offset voltage drift with temperature is seen in the Langan Patent, U.S. Pat. No. 3,757,239, which discloses a drift reduction method for a D.C. amplifier having bipolar input transistors. In this patent, the offset voltage is initially trimmed by a potentiometer 19, which adjusts the voltage difference between the emitters of input transistors 10 and 11 to exactly zero. Subsequently, trim resistors 12 and 13 are shorted and the amplifier is subjected to a known temperature change. The drift characteristic of the amplifier is measured and then utilized to determine the temperature coefficients of the trim resistors. More specifically, at least one of the trim resistors 12 or 13 is provided with an opposite polarity temperature coefficient with respect to the temperature coefficient of the offset voltage so as to minimize the overall amplifier drift.
The Langan patent, thus, shows the use of a resistive network in the emitter load of a differential amplifier to reduce offset voltage drift. However, the Langan method requires two separate steps: the first step serving to trim the offset voltage through resistor 10, and the second step to determine the proper temperature characteristics of the trim resistors 12 and 13. Furthermore, the Langan circuit requires the use of an additional high gain feedback loop to stabilize the collector currents of the input transistors 10 and 11. The need for an additional method step in Langan, as well as the extra circuitry described therein, limits the flexibility of this trimming scheme.
Summarizing the scope of the prior art, the trimming of differential amplifier offset voltage without increasing the offset voltage drift is taught by the Russell patent. However, as noted above, the Russell circuit is not efficient where component mismatch exists in the offset adjustment circuit. The Langan patent also discloses a circuit for reducing offset voltage drift but requires a trimming scheme with two separate steps and the use of additional circuitry.
Therefore, there exists a need to provide a post-trim offset voltage drift adjustment circuit for a differential amplifier which is less sensitive to active component mismatch in the adjustment circuit and which only requires a single trim step at a single temperature.